Bulk CMOS technology is susceptible to being triggered into a latch-up (a high current state) condition due to the presence of parasitic bipolar transistor structures comprising a combination of NPN & PNP bipolar transistors that are coupled to form a parasitic PNPN structure. This parasitic PNPN structure is similar to a Silicon Controlled Rectifier (SCR) circuit.
When CMOS devices are exposed to high energy particles, such as heavy ions, protons, or neutrons, or light, CMOS devices are generally susceptible to adverse radiation effects such as Single Event Latch-up (SEL). There are various known ways to mitigate the SEL risk, including changing the IC layout using annular (race track) components, modifying the process, or using a select starting material such as an epi layer on a P+ substrate, or silicon on insulator or similar starting material that provides dielectric isolation between the devices.
Reducing the substrate resistance (Rsub) and Nwell resistance in a P-substrate starting material will produce lower voltage drops for the same current and thus mitigate the SCR, which minimizes the chance for latch-up of the SCR. Reducing the gain product (or β) of the NPN and PNP bipolar devices in the SCR feedback loop to less than one (1) can stop latch-up of the SCR. This can be accomplished by moving the Nwell and N+ Source/Drain spacing further apart, which increases the base width of the bipolar devices and thus reduces the bipolar gain. Guard rings are commonly used to reduce the parasitic impedance in the collector circuits of the parasitic SCR.
Another approach involves creating blanket buried guard rings or buried layers after transistor formation using high dose, very high energy implantation. This approach is low throughput due to a time consuming implant process, and results in a leakage path formed between the isolated wells and the substrate, such as between the Pwells and the p-substrate for a p− starting material. Moreover, this approach may increase gate dielectric integrity risks, and being a blanket doping process is only applicable to twin-well CMOS devices. Accordingly, none of these known approaches provide a cost-effective SEL solution that addresses existing bulk CMOS IC designs for twin-well CMOS devices, and none of these approaches are applicable to triple-well or vertical isolated CMOS devices.